GATE 2025 CS (CS2) – Question 56

Computer Organization and Architecture · Instruction Pipelining and Pipeline Hazards · 2 marks · Numerical answer

A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)

Practise this question in The GATE Grind →

Show answer and explanation

Correct answer: 261.04

Explanation

Clock cycle = max stage delay + latch delay = 250 + 10 = 260 ns. Total time = (5 + 999) × 260 ns = 261040 ns = 261.04 µs.