GATE 2024 CS (CS2) – Question 61

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA has 150 distinct instructions, equally divided into R-type and I-type. R-type format: OPCODE, UNUSED, DST Register, SRC Register1, SRC Register 2. I-type format: OPCODE, DST Register, SRC Register, immediate value/address. In the OPCODE, 1 bit distinguishes I-type and R-type and the remaining bits indicate the operation. The processor has 50 architectural registers and all register fields are of equal size. Let $X$ be the number of bits for the UNUSED field, $Y$ for the OPCODE field, and $Z$ for the immediate value/address field. The value of $X+2Y+Z$ is ________