GATE 2023 CS – Question 42

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high. [Figure: 2-to-4 decoder with inputs IA4 (MSB) and IA3 (LSB), outputs Q0–Q3 driving CS of blocks X1–X4; IA11–IA5 and IA2–IA0 go to the 10-bit Addr port.] The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?