GATE 2026 CS (CS2) – Question 57
A non-pipelined instruction execution unit operating at 1.6 GHz takes an average of 5 clock cycles per instruction. A pipelined redesign could operate only at 1.2 GHz because of pipeline overheads. While executing a program on the pipelined design, 30% of instructions encounter a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one is __________. (rounded off to two decimal places)
Note: $1\text{ G}=10^9$.
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Correct answer: 2.34
Explanation
In the non-pipelined design, each instruction takes 5 cycles at 1.6 GHz, so the average time per instruction is $$\frac{5}{1.6\times10^9}=3.125\text{ ns}.$$ In the pipelined design, the ideal CPI is 1, but 30% of instructions incur a 2-cycle stall, so the average CPI is $$1+0.3\times2=1.6.$$ At 1.2 GHz, the average time per instruction is $$\frac{1.6}{1.2\times10^9}=1.333\overline{3}\text{ ns}.$$ Therefore, the speed-up is $$\frac{3.125}{1.333\overline{3}}\approx2.34.$$ Hence the answer is 2.34.