GATE 2026 CS (CS1) – Question 37
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input $P$ is 0, and the saturating down count when $P$ is 1. The counter is built as a synchronous sequential circuit using D flip-flops with inputs $D_1$ and $D_0$ for current states $Q_1, Q_0$. Which one of the following options corresponds to the minimal SOP expressions for $D_1$ and $D_0$?
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Correct answer: (B) $D_1 = \overline{P} Q_1 + \overline{P} Q_0 + Q_1 Q_0, \quad D_0 = \overline{P} \overline{Q}_0 + \overline{P} Q_1 + Q_1 \overline{Q}_0$
Explanation
From the truth table of the 2-bit saturating counter:
- When $P = 0$ (Up counter, saturating at 3):
- $00 \to 01$
- $01 \to 10$
- $10 \to 11$
- $11 \to 11$
- When $P = 1$ (Down counter, saturating at 0):
- $00 \to 00$
- $01 \to 00$
- $10 \to 01$
- $11 \to 10$
Minimizing $D_1(P, Q_1, Q_0)$ on a 3-variable K-map:
$D_1 = 1$ for minterms $m(1, 2, 3, 7)$:
Grouping yields $D_1 = \overline{P}Q_1 + \overline{P}Q_0 + Q_1Q_0$.
Minimizing $D_0(P, Q_1, Q_0)$ on a 3-variable K-map:
$D_0 = 1$ for minterms $m(0, 2, 3, 6)$:
Grouping yields $D_0 = \overline{P}\overline{Q}_0 + \overline{P}Q_1 + Q_1\overline{Q}_0$.
This matches option (B).