GATE 2026 CS (CS1) – Question 54

Operating System · Memory Management and Virtual Memory · 2 marks · Multiple choice

Consider a system that has a cache memory unit and a memory management unit (MMU) with a Translation Lookaside Buffer (TLB). Which one of the following combinations of events is IMPOSSIBLE?

TLB miss, Page table hit, Cache hit
TLB hit, Page table miss, Cache hit
TLB miss, Page table miss, Cache hit
TLB miss, Page table miss, Cache miss

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Show answer and explanation

Correct answer: (B) TLB hit, Page table miss, Cache hit

Explanation

The TLB is a high-speed hardware cache for the page table. A **TLB hit** means that the valid translation mapping (Virtual Page Number $\to$ Physical Frame Number) is currently cached in the TLB.
The TLB can only contain entries that are validly present in the page table (in main memory). Therefore, if a TLB hit occurs, the corresponding page mapping MUST be present in the page table.
A **Page table miss** (page fault) means the requested page is not present in main memory. A page translation cannot simultaneously be cached as valid in the TLB while being absent from the page table.
Hence, the combination **TLB hit, Page table miss** is completely IMPOSSIBLE in any memory hierarchy.

Therefore, option (B) is the impossible combination.