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GATE 2020 PH – Question 40

Electronics · Basics of digital logic circuits, combinational and sequential circuits, flip- flops, timers, counters, registers, A/D and D/A conversion. · 2 marks · Multiple choice

A four-bit ripple counter uses four flip-flops with J = K = 1; each Q output clocks the next flip-flop. Falling clock edges trigger changes. All outputs are low at $t=t_0$. For the input waveform shown, the outputs at $t=t_1$ are

Diagram for GATE 2020 PH question 40
  1. $Q_0=1,Q_1=0,Q_2=0,Q_3=0$
  2. $Q_0=0,Q_1=0,Q_2=0,Q_3=1$
  3. $Q_0=1,Q_1=0,Q_2=1,Q_3=0$
  4. $Q_0=0,Q_1=1,Q_2=1,Q_3=1$

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Correct answer: (B) $Q_0=0,Q_1=0,Q_2=0,Q_3=1$

Explanation

J = K = 1 makes each stage toggle on its active falling clock edge. Cascading the Q outputs produces a binary up counter with $Q_0$ the least significant bit. Eight falling edges occur between the marked times, so the counter advances from 0000 to 1000 in $Q_3Q_2Q_1Q_0$ order. Thus $Q_3=1$ and the other three outputs are zero, option B.

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