GATE 2023 BM – Question 18
An 8-bit successive-approximation ADC uses a 1 MHz clock. Starting and ending each conversion take one clock cycle each, in addition to the comparison cycles. Among the options, what is the maximum input frequency that can be sampled without aliasing?
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Correct answer: (C) 49.9 kHz
Explanation
Eight successive bit decisions plus two overhead cycles require ten clock cycles per conversion. Sampling rate is 1 MHz/10=100 ksample/s, so the input must be below fifty kilohertz. The maximum listed frequency below this limit is 49.9 kHz, C.