GATE 2015 CS – Question 53
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that $J = K = 1$ is the toggle mode and $J = K = 0$ is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
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Correct answer: (A) 0110110...
Explanation
Track the pair (D output, JK output), starting at (1, 0). At each clock edge the JK flip-flop toggles if D is 1 and holds if D is 0, and D copies the old JK output. Edge 1 gives (0, 1). Edge 2 gives (1, 1). Edge 3 gives (1, 0). Edge 4 gives (0, 1). Edge 5 gives (1, 1). Edge 6 gives (1, 0). The JK output sequence is 0, 1, 1, 0, 1, 1, 0, which repeats as 0110110...