The GATE Grind

GATE Digital Logic: Sequential Circuits – Previous Year Questions

11 GATE previous year questions on Sequential Circuits (Digital Logic, Computer Science) with answers and explanations, from every paper.

  1. GATE 2017 CS Q43 (2 marks, Multiple choice) – Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and…
  2. GATE 2016 CS Q18 (1 mark, Numerical answer) – We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to…
  3. GATE 2015 CS Q21 (1 mark, Multiple choice) – Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
  4. GATE 2015 CS Q53 (2 marks, Multiple choice) – A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected…
  5. GATE 2018 CS Q32 (1 mark, Numerical answer) – Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops (a serial chain with input…
  6. GATE 2026 CS (CS1) Q37 (2 marks, Multiple choice) – Consider a 2-bit saturating up/down counter that performs the saturating up count when the input P is 0, and the saturating down count when P is 1.…
  7. GATE 2025 CS (CS2) Q34 (1 mark, Numerical answer) – In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is…
  8. GATE 2025 CS (CS1) Q60 (2 marks, Numerical answer) – Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct…
  9. GATE 2023 CS Q21 (1 mark, Multiple choice) – The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. [Figure: 2-input MUX with inputs 0 and 1, select S,…
  10. GATE 2023 CS Q43 (2 marks, Multiple choice) – Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At…
  11. GATE 2021 CS Q38 (2 marks, Multiple choice) – Consider a 3-bit counter, designed using T flip-flops, with the clock going to T P; T P = R', T Q = P' (Q clocked by P' path), T R = Q' path as shown…