Two positive-edge-triggered T flip-flops have T=1. The external clock drives flip-flop 0, whose Q₀ output clocks flip-flop 1. Starting from Q₁Q₀=00, what is the sequence after successive external clock edges?
On the first edge Q₀ rises from zero to one, producing a rising edge at the second flip-flop, so Q₁ also toggles: 11. The next Q₀ transition is falling, leaving Q₁ unchanged: 10. The next rising Q₀ toggles Q₁ back to zero: 01. The fourth gives 00. Thus A.
More Sequential Circuits questions
GATE 2015 CS (CS2) Q17– Find the minimum number of JK flip-flops for a synchronous counter with output sequence…
GATE 2021 CS (CS2) Q38– A synchronous circuit replaces the first 1 of every maximal run of consecutive ones by 0,…
GATE 2026 CS (CS1) Q37– Consider a 2-bit saturating up/down counter that performs the saturating up count when the…
GATE 2025 CS (CS1) Q60– Consider the given sequential circuit designed using D-Flip-flops. The circuit is…
GATE 2025 CS (CS2) Q34– In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64…
GATE 2023 CS Q21– The output of a 2-input multiplexer is connected back to one of its inputs as shown in the…