GATE Digital Electronics: Number systems and combinational logic – Previous Year Questions
14 GATE previous year questions on Number systems and combinational logic (Digital Electronics, Instrumentation Engineering) with answers and explanations, from every paper.
- GATE 2021 IN Q41 – Boolean F(X,Y,Z)=(X+Y+Z)(X+Y+Z)(X+Y+Z)(X Y Z+X YZ+XYZ). Which expression is true?
- GATE 2021 IN Q45 – A 4×1 MUX realizes Boolean F(X,Y,Z,W). S 0 is the LSB and S 1 the MSB selector, connected as shown. I 0–I 3 are its inputs. Its canonical…
- GATE 2022 IN Q21 – The logic block shown has output F given by .
- GATE 2022 IN Q23 – The output F of the digital circuit shown can be written in the form(s) .
- GATE 2022 IN Q48 – A=a 1a 0 and B=b 1b 0 are unsigned two-bit binary numbers. Boolean F(a 1,a 0,b 1,b 0) is 1 exactly when A>B. Its minimized form is .
- GATE 2023 IN Q17 – Match XOR operations i–iv to results p–s, where X is a Boolean input. Operations: i. X X; ii. X X; iii. X0; iv. X1. Results: p. 1; q. 0; r. X; s. X.
- GATE 2023 IN Q22 – Choose the fastest logic family among the following:
- GATE 2023 IN Q40 – Simplify F(W,X,Y,Z)=(4,5,10,11,12,13,14,15) using the minimum number of terms and fewest literals per term.
- GATE 2023 IN Q41 – For the given digital circuit, A = B = 1. Assume that AND, OR, and NOT gates have propagation delays of 10 ns, 10 ns, and 5 ns respectively. All lines…
- GATE 2024 IN Q16 – The simplified form of the Boolean function F=(A+ A B)+ A(A+ B)C is
- GATE 2025 IN Q17 – The minimized Boolean expression Y(P,Q,R) implemented by the shown multiplexer circuit is
- GATE 2025 IN Q18 – The 4-bit signed two’s-complement result of (5) 10+(5) 10 is
- GATE 2025 IN Q29 – A Boolean function is X= A B+ A C. The reduced form of X is
- GATE 2026 IN Q55 – Which of the following functions represent(s) the output of the CMOS logic gate shown in the circuit below?