GATE 2011 CS (CS1) – Question 38
An interrupt routine on a sequential nonpipelined processor initializes an address register and count=500, then repeats: load byte from device; store at address; increment address; decrement count; branch if count≠0. Each load/store takes two cycles; other statements take one. DMA instead costs twenty setup/overhead cycles plus two cycles per byte. Find approximate DMA speedup.
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Correct answer: (A) 3.4
Explanation
The loop costs 2+2+1+1+1=7 cycles per byte. Two initializations add two cycles, so interrupt transfer takes 500×7+2=3502 cycles. DMA takes 20+500×2=1020 cycles. Speedup is 3502/1020≈3.43, closest to 3.4, A.