GATE 2021 CS (CS2) – Question 30

Computer Organization and Architecture · I/O Interface: Interrupt and DMA · 1 mark · Numerical answer

A 2 MHz processor supports cycle-stealing DMA. The DMA transfers one 8-bit character in one CPU cycle at regular intervals. If DMA uses 0.5% of CPU cycles, find the data-transfer rate in bits/s.

Practise this question in The GATE Grind →

Show answer and explanation

Correct answer: 80000 to 80000

Explanation

The processor provides 2×10⁶ cycles per second. DMA takes 0.005 of them, or ten thousand cycles per second. At eight bits transferred per stolen cycle, the data rate is 10000×8=80000 bits/s.

More I/O Interface: Interrupt and DMA questions

GATE 2026 CS (CS2) Q18 – Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In…
GATE 2025 CS (CS1) Q11 – Suppose a program is running on a non-pipelined single processor computer system. The…
GATE 2024 CS (CS1) Q15 – Which one of the following statements is FALSE?
GATE 2024 CS (CS2) Q11 – Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1…
GATE 2023 CS Q34 – A keyboard connected to a computer is used at a rate of 1 keystroke per second. The…
GATE 2022 CS Q17 – Which one of the following facilitates transfer of bulk data from hard disk to main memory…

All I/O Interface: Interrupt and DMA questions →