GATE Computer Organization and Architecture: I/O Interface: Interrupt and DMA – Previous Year Questions
9 GATE previous year questions on I/O Interface: Interrupt and DMA (Computer Organization and Architecture, Computer Science) with answers and explanations, from every paper.
- GATE 2016 CS Q41 – The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main…
- GATE 2018 CS Q19 – The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes…
- GATE 2026 CS (CS2) Q18 – Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In a non-vectored interrupt mechanism, it usually takes more…
- GATE 2025 CS (CS1) Q11 – Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt…
- GATE 2024 CS (CS2) Q11 – Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at…
- GATE 2024 CS (CS1) Q15 – Which one of the following statements is FALSE?
- GATE 2023 CS Q34 – A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to…
- GATE 2022 CS Q17 – Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?
- GATE 2020 CS Q13 – Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored…