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GATE 2024 CS (CS2) – Question 11

Computer Organization and Architecture · I/O Interface: Interrupt and DMA · 1 mark · Multiple choice

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?

  1. 2,56,000
  2. 3,200
  3. 25,60,000
  4. 32,000

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Correct answer: (A) 2,56,000

Explanation

DMA cycles per second = 1% of 4×10^6 = 40,000. Each transfers 8 bytes = 64 bits, so rate = 40,000 × 64 = 2,560,000 bits/s.