The GATE Grind

GATE 2020 CS – Question 13

Computer Organization and Architecture · I/O Interface: Interrupt and DMA · 1 mark · Multiple choice

Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.

II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.

III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.

IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

  1. I and II only
  2. I and IV only
  3. I and III only
  4. III only

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Correct answer: (C) I and III only

Explanation

I and III are correct. II is false because a vectored interrupt supplies the ISR address directly, so no polling is needed. IV is false because only one bus master is active at a time.