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GATE 2020 CS – Question 14

Computer Organization and Architecture · Instruction Set and Addressing Modes · 1 mark · Multiple choice

Consider the following data path diagram. [Figure: single-bus data path with MAR, MDR, IR, PC, register file R0-R7, TEMP1, TEMP2 and ALU]

Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. R2_r, TEMP1_r, ALU_add, TEMP2_w
2. R1_r, TEMP1_w
3. PC_r, MAR_w, MEM_r
4. TEMP2_r, R0_w
5. MDR_r, IR_w

Which one of the following is the correct order of execution of the above steps?

Diagram for GATE 2020 CS question 14
  1. 2, 1, 4, 5, 3
  2. 1, 2, 4, 3, 5
  3. 3, 5, 2, 1, 4
  4. 3, 5, 1, 2, 4

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Correct answer: (C) 3, 5, 2, 1, 4

Explanation

Fetch comes first: step 3 (PC to MAR, memory read) then step 5 (MDR to IR). Then R1 is loaded into TEMP1 (step 2), R2 is added via the ALU into TEMP2 (step 1), and TEMP2 is written to R0 (step 4). Order: 3, 5, 2, 1, 4.