GATE Computer Organization and Architecture: Instruction Set and Addressing Modes – Previous Year Questions
16 GATE previous year questions on Instruction Set and Addressing Modes (Computer Organization and Architecture, Computer Science) with answers and explanations, from every paper.
- GATE 2017 CS Q21 – Consider the C struct defined below: The base address of `student` is available in register R1. The field `student.grade` can be accessed efficiently…
- GATE 2017 CS Q59 – Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing…
- GATE 2015 CS Q22 – For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2)…
- GATE 2018 CS Q15 – Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III.…
- GATE 2018 CS Q61 – A processor has 16 integer registers (R0, R1, ..., R15) and 64 floating point registers (F0, F1, ..., F63). It uses a 2-byte instruction format. There…
- GATE 2026 CS (CS2) Q44 – Consider a processor that has 16 general-purpose registers and uses a 2-byte instruction format for all instructions. Variable-sized opcodes are…
- GATE 2026 CS (CS1) Q14 – Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II: List I: P. Immediate…
- GATE 2026 CS (CS1) Q15 – Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any…
- GATE 2025 CS (CS2) Q28 – Which of the following is/are part of an Instruction Set Architecture of a processor?
- GATE 2025 CS (CS1) Q37 – A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of…
- GATE 2024 CS (CS2) Q57 – A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode…
- GATE 2024 CS (CS2) Q61 – A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA has 150 distinct instructions, equally divided into…
- GATE 2023 CS Q41 – Consider the given C-code and its corresponding assembly code, with a few operands U1–U4 being unknown. The memory is byte-addressable. Which one of…
- GATE 2021 CS Q65 – Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location…
- GATE 2020 CS Q14 – Consider the following data path diagram. [Figure: single-bus data path with MAR, MDR, IR, PC, register file R0-R7, TEMP1, TEMP2 and ALU] Consider an…
- GATE 2020 CS Q54 – A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains…