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GATE 2025 CS (CS2) – Question 28

Computer Organization and Architecture · Instruction Set and Addressing Modes · 1 mark · Multiple select

Which of the following is/are part of an Instruction Set Architecture of a processor?

  1. The size of the cache memory
  2. The clock frequency of the processor
  3. The number of cache memory levels
  4. The total number of registers

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Correct answer: (D) The total number of registers

Explanation

The ISA defines the programmer-visible interface: instructions, registers, addressing modes and data types. Cache size, cache levels and clock frequency are microarchitecture/implementation details.