The GATE Grind

GATE 2026 CS (CS1) – Question 14

Computer Organization and Architecture · Instruction Set and Addressing Modes · 1 mark · Multiple choice

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

List I:

P. Immediate addressing

Q. Direct addressing

R. Register indirect addressing

S. Base-index addressing

List II:

1. Pointer dereference

2. Array element access

3. Global variable

4. Constant value

  1. P–4, Q–3, R–1, S–2
  2. P–4, Q–2, R–1, S–3
  3. P–1, Q–4, R–3, S–2
  4. P–2, Q–3, R–1, S–4

Practise this question in The GATE Grind →

Show answer and explanation

Correct answer: (A) P–4, Q–3, R–1, S–2

Explanation

Matching addressing modes to corresponding programming language elements:
- **P. Immediate addressing**: The operand value is embedded directly within the instruction; this corresponds to a compile-time **Constant value (4)** (e.g. `x = 5`).
- **Q. Direct addressing**: The effective address is provided directly in the instruction; used for statically allocated **Global variables (3)**.
- **R. Register indirect addressing**: A register holds the memory address of the operand; this implements **Pointer dereference (1)** (e.g. `*ptr`).
- **S. Base-index addressing**: The effective address is the sum of a base register and an index register (scaled by element size); this directly implements **Array element access (2)** (e.g. `arr[i]`).

Matching: P-4, Q-3, R-1, S-2. Therefore, option (A) is correct.