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GATE 2026 CS (CS1) – Question 15

Computer Organization and Architecture · Instruction Set and Addressing Modes · 1 mark · Multiple choice

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand, and the other operands are the source operands. In order to compute $Z = X + Y$, where $X, Y, Z$ are memory locations, which of the following instruction sequences is correct?

  1. ADD Z, X, Y
  2. LOAD R0, X; ADD Z, R0, Y
  3. ADD R0, X, Y; STORE Z, R0
  4. LOAD R0, X; LOAD R1, Y; ADD R2, R0, R1; STORE Z, R2

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Correct answer: (D) LOAD R0, X; LOAD R1, Y; ADD R2, R0, R1; STORE Z, R2

Explanation

In a strict load-store architecture (such as RISC):
- Arithmetic and logic instructions (e.g. `ADD`) can ONLY operate on processor registers; they cannot directly take memory addresses as operands.
- Memory can only be accessed through dedicated `LOAD` and `STORE` instructions.

To compute $Z = X + Y$:
1. Load value at memory address $X$ into register $R0$: `LOAD R0, X`
2. Load value at memory address $Y$ into register $R1$: `LOAD R1, Y`
3. Perform register-to-register addition: `ADD R2, R0, R1` (storing sum in $R2$)
4. Store the result register $R2$ into memory location $Z$: `STORE Z, R2`

Therefore, option (D) is the only correct sequence.