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GATE 2026 CS (CS1) – Question 16

Computer Organization and Architecture · Instruction Pipelining and Pipeline Hazards · 1 mark · Multiple choice

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

  1. Read-after-read
  2. Read-after-write
  3. Write-after-read
  4. Write-after-write

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Show answer and explanation

Correct answer: (B) Read-after-write

Explanation

In an in-order instruction execution pipeline:
- **Read-After-Write (RAW)** is a true data dependency. If instruction $I_2$ attempts to read a register before instruction $I_1$ writes its computed value to that register, $I_2$ reads stale data. This causes a true data hazard.
- **Read-After-Read (RAR)** is not a hazard since reading does not change data.
- **Write-After-Read (WAR)** and **Write-After-Write (WAW)** are anti-dependencies/output dependencies that do not cause hazards in standard in-order pipelines.

Therefore, option (B) is correct.