GATE 2024 CS (CS2) – Question 58

A non-pipelined unit at 2 GHz takes an average of 6 cycles per instruction of program P. The unit is redesigned as a 5-stage pipeline at 2 GHz with ideal throughput of 1 instruction per cycle. In program P, 20% instructions incur an average of 2 cycles stall due to data hazards and 20% incur an average of 3 cycles stall due to control hazards. The speedup (rounded off to one decimal place) of the pipelined design over the non-pipelined design is _________