GATE 2015 CS – Question 55
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is ________.
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Show answer and explanation
Correct answer: 3.18 to 3.22
Explanation
The non-pipelined processor takes $\frac{4}{2.5} = 1.6$ ns per instruction. With no stalls the pipelined processor finishes one instruction per cycle, which takes $\frac{1}{2} = 0.5$ ns. The speedup is $\frac{1.6}{0.5} = 3.2$. The official key accepts 3.2 as the answer.