GATE 2017 CS – Question 60
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is ________.
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Correct answer: 1.50 to 1.52
Explanation
The clock period is the slowest stage plus the 2 ns buffer. For NP that is $20 + 2 = 22$ ns, and 20 instructions on 5 stages take $(5 + 19) \times 22 = 528$ ns. For EP the stages are 5, 4, 12, 8, 10, 3, so the slowest is 12 and the period is 14 ns. With 6 stages the time is $(6 + 19) \times 14 = 350$ ns. The speedup is $\frac{528}{350} = 1.51$.