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GATE 2014 CS (CS3) – Question 19

Computer Organization and Architecture · Instruction Pipelining and Pipeline Hazards · 1 mark · Multiple choice

Pipeline registers have zero latency. Stage latencies (ns) are P1: 1,2,2,1; P2: 1,1.5,1.5,1.5; P3: 0.5,1,1,0.6,1; P4: 0.5,0.5,1,1,1.1. Which processor has the highest peak clock frequency?

  1. P1
  2. P2
  3. P3
  4. P4

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Show answer and explanation

Correct answer: (C) P3

Explanation

With zero register overhead, clock period is the largest stage latency. The four periods are2,1.5,1,1.1ns. The smallest period1ns belongs to **P3,C**, giving1GHz. Total stage latency does not determine peak clock frequency.