A 3 GHz three-stage pipeline has latencies $\tau_1=3\tau_2/4=2\tau_3$. The longest stage is split into two equal stages. Ignoring register delay, find the new frequency in GHz.
Express times as τ₂=4τ₁/3 and τ₃=τ₁/2. The old bottleneck is τ₂. After splitting it, its two stages each take 2τ₁/3, making τ₁ the new bottleneck. Frequency improves by 4/3, from 3 GHz to 4 GHz.
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