GATE 2011 CS (CS1) – Question 51
Four pipeline stages take 5,6,11,8 ns. Registers between stages and after the last each add one ns. Under ideal steady-state conditions, find approximate speedup over nonpipelined operation.
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Correct answer: (B) 2.5
Explanation
Nonpipelined combinational time is 5+6+11+8=30 ns. The pipeline clock is set by the slowest stage plus register delay, 11+1=12 ns. Ideal steady-state throughput speedup is 30/12=2.5, B. Stage imbalance and register overhead prevent the factor from reaching four.