GATE 2021 CS (CS2) – Question 63
A five-stage pipeline has IF,ID,EX,MEM,WB. All stages take one cycle except EX: ADD takes one and MUL two. ID decodes and reads registers. Instruction sequence is ADD,MUL,ADD,MUL,ADD,MUL,ADD,MUL. Each MUL depends on the previous ADD; each ADD except the first depends on the previous MUL. Ignore pipeline-register latency. Find speedup = time without forwarding / time with forwarding, rounded to two decimals.
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Correct answer: 1.87 to 1.88
Explanation
With forwarding, dependent instructions can use the preceding EX result; total duration is the eight instructions plus four pipeline fill/drain cycles plus four extra MUL cycles, giving sixteen cycles. Without forwarding, each dependent instruction must wait until its predecessor’s WB result is available for ID, adding two cycles per one of seven dependencies under the source’s same-cycle write/read convention. Total thirty cycles. Speedup=30/16=1.875, approximately 1.88, in the official 1.87–1.88 interval.