GATE Computer Organization and Architecture: Instruction Pipelining and Pipeline Hazards – Previous Year Questions
15 GATE previous year questions on Instruction Pipelining and Pipeline Hazards (Computer Organization and Architecture, Computer Science) with answers and explanations, from every paper.
- GATE 2017 CS Q60 – Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and…
- GATE 2016 CS Q42 – The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a…
- GATE 2015 CS Q55 – Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a…
- GATE 2018 CS Q60 – The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform…
- GATE 2026 CS (CS2) Q57 – A non-pipelined instruction execution unit operating at 1.6 GHz takes an average of 5 clock cycles per instruction. A pipelined redesign could operate…
- GATE 2026 CS (CS1) Q16 – Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
- GATE 2026 CS (CS1) Q60 – The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic…
- GATE 2025 CS (CS2) Q56 – A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10…
- GATE 2024 CS (CS2) Q31 – An instruction format has the structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2. Consider the sequence: I1: DIV R3,…
- GATE 2024 CS (CS2) Q58 – A non-pipelined unit at 2 GHz takes an average of 6 cycles per instruction of program P. The unit is redesigned as a 5-stage pipeline at 2 GHz with…
- GATE 2024 CS (CS1) Q30 – Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback…
- GATE 2023 CS Q33 – Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages,…
- GATE 2022 CS Q61 – A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any…
- GATE 2021 CS Q63 – A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay…
- GATE 2020 CS Q53 – Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline…