GATE 2018 CS – Question 60

Computer Organization and Architecture · Instruction Pipelining and Pipeline Hazards · 2 marks · Numerical answer

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is ________.

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Correct answer: 219

Explanation

The PO stage is the bottleneck: it processes the instructions one after another for a total of $40\times3+35\times2+25\times1=215$ cycles. Adding the IF, ID, OF stages before the first PO (3 cycles) and the WB stage after the last (1 cycle) gives $215+4=219$ cycles.