An L1 cache has four-word blocks and 2 ns access time. L2 has sixteen-word blocks and 20 ns access time. Main memory takes 200 ns. Each connecting bus transfers four words per transfer. On an L1 miss and L2 hit, how long does it take to load the required L1 block from L2?
An L1 block is four words, so one bus transfer suffices. The L2 read takes twenty nanoseconds and filling the L1 block takes two. Total transfer/fill time is 20+2=22 ns, C, under the sequential timing model in the question.
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