GATE Computer Organization and Architecture: Memory Interfacing and Hierarchy – Previous Year Questions
29 GATE previous year questions on Memory Interfacing and Hierarchy (Computer Organization and Architecture, Computer Science) with answers and explanations, from every paper.
- GATE 2017 CS Q35 – Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this…
- GATE 2017 CS Q61 – Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which…
- GATE 2017 CS Q64 – A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of…
- GATE 2016 CS Q19 – A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of…
- GATE 2018 CS Q33 – A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is…
- GATE 2018 CS Q44 – The size of the physical address space of a processor is 2P bytes. The word length is 2W bytes. The capacity of cache memory is 2N bytes. The size of…
- GATE 2019 CS Q11 – A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable…
- GATE 2019 CS Q12 – The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by…
- GATE 2019 CS Q43 – Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable.…
- GATE 2019 CS Q55 – A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock.…
- GATE 2026 CS (CS2) Q52 – Consider a system with a processor and a 4 KB direct-mapped cache with block size 16 bytes. The system has a 16 MB physical memory. Four words P, Q,…
- GATE 2026 CS (CS2) Q56 – Consider a system with 1 MB physical memory and word length 1 byte. The system uses a direct-mapped cache, with block numbers starting from 0. The…
- GATE 2026 CS (CS1) Q38 – The size of the physical address space of a processor is 232 bytes. The capacity of a cache memory unit is 223 bytes. The cache block size is 128…
- GATE 2025 CS (CS2) Q55 – Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the…
- GATE 2025 CS (CS1) Q36 – Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and…
- GATE 2025 CS (CS1) Q53 – A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it…
- GATE 2024 CS (CS2) Q53 – Consider a disk with rotation speed of 6000 RPM, average seek time of 5 milliseconds, 500 sectors/track, 512-byte sectors. A file has content stored…
- GATE 2024 CS (CS1) Q53 – Consider two set-associative cache architectures: WBC (write back policy) and WTC (write through policy). Both use LRU replacement. The cache is…
- GATE 2024 CS (CS1) Q54 – Consider a 512 GB hard disk with 32 storage surfaces. There are 4096 sectors per track and each sector holds 1024 bytes of data. The number of…
- GATE 2024 CS (CS1) Q56 – A given program has 25% load/store instructions. The ideal CPI without memory stalls is 2. The program exhibits 2% miss rate on instruction cache and…
- GATE 2023 CS Q42 – A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip…
- GATE 2023 CS Q64 – An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX,…
- GATE 2022 CS Q24 – Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a…
- GATE 2022 CS Q33 – A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss…
- GATE 2022 CS Q54 – Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length…
- GATE 2021 CS Q32 – Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer system has a direct-mapped cache of size 32…
- GATE 2020 CS Q30 – If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of…
- GATE 2020 CS Q31 – A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss,…
- GATE 2020 CS Q40 – A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block…