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GATE 2022 CS – Question 24

Computer Organization and Architecture · Memory Interfacing and Hierarchy · 1 mark · Multiple select

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

  1. Each cache block in WB and WT has a dirty bit.
  2. Every write hit in WB leads to a data transfer from cache to main memory.
  3. Eviction of a block from WT will not lead to data transfer from cache to main memory.
  4. A read miss in WB will never lead to eviction of a dirty block from WB.

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Show answer and explanation

Correct answer: (A) Each cache block in WB and WT has a dirty bit.; (B) Every write hit in WB leads to a data transfer from cache to main memory.; (D) A read miss in WB will never lead to eviction of a dirty block from WB.

Explanation

A is false because write-through needs no dirty bit. B is false because write-back defers the write until eviction. D is false because a read miss can evict a dirty block, which is then written back. C is true.