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GATE 2022 CS – Question 54

Computer Organization and Architecture · Memory Interfacing and Hierarchy · 2 marks · Multiple select

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

  1. Every access to S is a hit.
  2. Once P is brought to the cache it is never evicted.
  3. At the end of the execution only R and S reside in the cache.
  4. Every access to R evicts Q from the cache.

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Correct answer: (A) Every access to S is a hit.; (B) Once P is brought to the cache it is never evicted.; (D) Every access to R evicts Q from the cache.

Explanation

The cache has 32 blocks, so the index is 5 bits. P and S share the same block (index 9), so S always hits after P and that block is never evicted. Q and R map to index 10 with different tags, so each R evicts Q and each Q evicts R. C is false because the P/S block stays resident along with R.