GATE 2019 CS – Question 12
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by $A_{15}$ to $A_0$. What is the range of addresses (in hexadecimal) of the memory system that can enable the chip select (CS) signal?
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Correct answer: (A) C800 to CFFF
Explanation
The AND gate has inverted inputs on $A_{13}$ and $A_{12}$, so CS is active for $A_{15}A_{14}A_{13}A_{12}A_{11}=11001$. The remaining 11 address lines run from all 0s to all 1s, giving $1100\ 1000\ 0000\ 0000=$ C800 to $1100\ 1111\ 1111\ 1111=$ CFFF.