L₁ and L₂ cache access times are 1 and 8 cycles. L₂-to-main-memory miss penalty is 18 cycles. L₁ miss rate is twice L₂ miss rate. AMAT is 2 cycles. Find the respective miss rates.
Let the L₂ local miss rate be m, so L₁ misses with 2m. Then $2=1+2m(8+18m)$, giving 36m²+16m−1=0. Its positive root is 1/18≈0.05556; L₁ rate is 1/9≈0.11111. Hence A.
More Memory Interfacing and Hierarchy questions
GATE 2017 CS (CS2) Q55– I-cache has (read time 2 ns, hit ratio 0.8), D-cache (2 ns,0.9), L₂-cache (8 ns,0.9).…
GATE 2017 CS (CS2) Q63– A byte-addressable main memory has 2³² bytes, divided into 32-byte blocks. A direct-mapped…
GATE 2012 CS (CS1) Q64– A computer has a 256 KB, four-way set-associative, write-back data cache, 32-byte blocks…
GATE 2012 CS (CS1) Q65– A computer has a 256 KB, four-way set-associative, write-back data cache, 32-byte blocks…
GATE 2013 CS (CS1) Q30– A k-way cache has v sets of k consecutive lines, with set s preceding s+1. Memory blocks…
GATE 2013 CS (CS1) Q63– Virtual addresses are 46 bits, physical addresses 32 bits. A three-level page table has…