GATE 2024 CS (CS1) – Question 56

Computer Organization and Architecture · Memory Interfacing and Hierarchy · 2 marks · Numerical answer

A given program has 25% load/store instructions. The ideal CPI without memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache is _________

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Correct answer: 3

Explanation

Stall cycles per instruction = 0.02·100 + 0.25·0.08·100 = 2 + 2 = 4. Real CPI = 2+4 = 6. Speedup with perfect cache = 6/2 = 3.00.