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GATE 2018 EC – Question 42

Digital Circuits · Semiconductor Memories · 2 marks · Multiple choice

A $2\times2$ ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation in the circuit above, what are the bits corresponding to $D_{ij}$ (where $i=0$ or 1 and $j=0$ or 1) stored in the ROM?

Diagram for GATE 2018 EC question 42
  1. $\begin{bmatrix}1&0\\0&1\end{bmatrix}$
  2. $\begin{bmatrix}0&1\\1&0\end{bmatrix}$
  3. $\begin{bmatrix}1&0\\1&0\end{bmatrix}$
  4. $\begin{bmatrix}1&1\\0&0\end{bmatrix}$

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Show answer and explanation

Correct answer: (A) $\begin{bmatrix}1&0\\0&1\end{bmatrix}$

Explanation

A diode connects a word line to a bit line only where a 1 is stored. The figure has a diode between W0 and B0 and another between W1 and B1, so $D_{00}=1$ and $D_{11}=1$ and the other two bits are 0.