The GATE Grind

GATE 2014 EC (EC3) – Question 50

Digital Circuits · Semiconductor Memories · 2 marks · Multiple choice

WL denotes word line and BL bit line. Which diagram is an SRAM cell?

Diagram for GATE 2014 EC (EC3) question 50
  1. Diagram A
  2. Diagram B
  3. Diagram C
  4. Diagram D

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Show answer and explanation

Correct answer: (B) Diagram B

Explanation

A six-transistor SRAM cell requires two cross-coupled CMOS inverters and two NMOS access devices controlled by the word line, connecting complementary storage nodes to BL and BL̄. **B** has these devices and cross-coupled connections. A lacks the necessary cross-coupling, while C and D use incorrect transistor types in the inverter or access positions.