GATE 2024 IN – Question 42
The positive-edge-triggered D flip-flops shown are initially reset to $Q=0$. Gates and multiplexers have no propagation delay. After reset, clock pulses are applied; the waveforms of DIN, S, and CLK are shown. Assuming no timing violations, the output sequence from the third through fifth clocks, $Y_3Y_4Y_5$, is
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Correct answer: (A) 001
Explanation
With $S=1$, the stages shift; with $S=0$, they hold. Starting at 000, the states after clocks 1, 2, 3 are 100, 110, 011. Clock 4 holds 011; clock 5 shifts to 101. The gate network implements $Y=\overline{Q_2(\bar Q_1+Q_3)}$. Evaluating it gives $Y_3=0,Y_4=0,Y_5=1$.
Answer: **001, A**.