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GATE 2014 EC (EC4) – Question 24

Digital Circuits · Data Converters · 1 mark · Multiple choice

For a given sample-and-hold circuit, increasing the hold capacitor causes ______.

  1. droop rate and acquisition time to decrease
  2. droop rate to decrease and acquisition time to increase
  3. droop rate to increase and acquisition time to decrease
  4. droop rate and acquisition time to increase

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Show answer and explanation

Correct answer: (B) droop rate to decrease and acquisition time to increase

Explanation

For a fixed leakage current, droop rate is |dV/dt|=Ileak/C, so a larger capacitor reduces droop. Charging it through the fixed acquisition resistance takes longer because the RCtime constant increases. Therefore **droop decreases and acquisition time increases,B**.