The synchronous sequential circuit starts with $Q_AQ_BQ_C=Q_A\prime Q_B\prime Q_C\prime=100$, for which Z=0. The minimum number of clocks before Z becomes zero again is ________.
The upper register feeds QC back directly and cycles 100→010→001→100. The lower feeds the complement of its last bit back and cycles 100→110→111→011→001→000→100.
The XORs compare corresponding bits and their outputs are ORed, so Z=0 exactly when the two 3-bit words match.
For clocks 1 through 5 their word pairs are (010,110), (001,111), (100,011), (010,001), (001,000), all unequal. At clock 6 both return to 100. Thus **6 cycles**.
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