GATE 2015 EE – Question 47

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 2 marks · Numerical answer

The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting state of $Q_2 Q_1 Q_0 = 000$. This state $Q_2 Q_1 Q_0 = 000$ will repeat after ________ number of cycles of the clock CLK.

Three negative edge triggered J-K flip-flops with $J_0 = K_0 = 1$, and $J_1$, $K_1$, $J_2$, $K_2$ wired to outputs of the other flip-flops so the counter does not follow the plain binary sequence. All three share the clock CLK.

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Correct answer: 6

Explanation

Stepping the three flip-flops through the clock edges from the state 000 and using the connections in the figure, the counter passes through six different states before returning to 000. So the state repeats after 6 clock cycles, which matches the official key.