The GATE Grind

GATE 2014 EE (EE1) – Question 60

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 2 marks · Multiple choice

Which logic circuit realizes F represented by the Karnaugh map shown?

Diagram for GATE 2014 EE (EE1) question 60
  1. Circuit A
  2. Circuit B
  3. Circuit C
  4. Circuit D

Practise this question in The GATE Grind →

Show answer and explanation

Correct answer: (C) Circuit C

Explanation

Group the upper-row cells AB=00and01to get ĀC̄. Group the lower-row cells AB=01and11to get BC. Thus F=ĀC̄+BC. Circuit **C** implements the two complemented-input product and the BCproduct followed by OR. The shared01column is covered by both groups as needed.