The GATE Grind

GATE 2017 EE – Question 47

Analog and Digital Electronics · VCOs and timers, combinatorial and sequential logic circuits, multiplexers, demultiplexers · 2 marks · Multiple choice

The logical gate implemented using the circuit shown below where, $V_1$ and $V_2$ are inputs (with 0 V as digital 0 and 5 V as digital 1) and $V_{OUT}$ is the output, is

A 5 V supply feeds a $1\ \text{k}\Omega$ resistor, whose lower end is the output node $V_{OUT}$. Two transistors $Q_1$ and $Q_2$, driven through $1\ \text{k}\Omega$ base resistors by $V_1$ and $V_2$, are connected in parallel between $V_{OUT}$ and ground.
  1. NOT
  2. NOR
  3. NAND
  4. XOR

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Show answer and explanation

Correct answer: (B) NOR

Explanation

If either input is high, its transistor turns on and pulls $V_{OUT}$ down to nearly 0 V. The output is high only when both transistors are off, which means both inputs are low. That is the NOR function.