Inputs D₀,D₁,D₂,D₃ and outputs X₀,X₁,V have rows: 0000→xx0; 1000→001; x100→011; xx10→101; xxx1→111. x is don’t-care, and V=1 iff input is valid. What circuit does this describe?
The outputs encode the index of the highest-priority asserted input, with D₃ overriding all lower inputs, then D₂,D₁,D₀. The validity bit distinguishes no asserted input. This is a priority encoder, A, rather than an ordinary encoder requiring one-hot inputs.
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