GATE Digital Logic: Combinational Circuits – Previous Year Questions
9 GATE previous year questions on Combinational Circuits (Digital Logic, Computer Science) with answers and explanations, from every paper.
- GATE 2016 CS Q40 – Consider the two cascaded 2-to-1 multiplexers as shown in the figure. [Figure: The first 2-to-1 MUX has input 0 tied to 0, input 1 tied to R, and…
- GATE 2019 CS Q40 – Consider three 4-variable functions f 1, f 2, and f 3, which are expressed in sum-of-minterms as f 1=(0,2,5,8,14), f 2=(2,3,6,8,14,15), f…
- GATE 2026 CS (CS2) Q59 – Consider the digital circuit shown below with two input lines A and B, two select lines S 0 and S 1, and an output line Y. The blocks Q and M…
- GATE 2025 CS (CS2) Q31 – Consider the following logic circuit diagram. [Figure: inputs X and Y feed a NAND gate, a NOT gate on X, and an AND gate taking X and Y; the three…
- GATE 2024 CS (CS1) Q28 – Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires…
- GATE 2024 CS (CS1) Q64 – Consider three 2-to-1 multiplexers M1, M2, M3. X1 and X2 are inputs of M1, X3 and X4 are inputs of M2, and A, B, C are the select lines of M1, M2, M3…
- GATE 2023 CS Q44 – A Boolean digital circuit is composed using two 4-input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0–X7 are…
- GATE 2022 CS Q40 – Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X,…
- GATE 2020 CS Q29 – A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content…