The GATE Grind

GATE 2019 EC – Question 23

Digital Circuits · Combinatorial Circuits · 1 mark · Multiple choice

A standard CMOS inverter is designed with equal rise and fall times ($\beta_n=\beta_p$). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin ($NM_L$) and the HIGH noise margin $NM_H$?

  1. $NM_L$ increases and $NM_H$ decreases.
  2. $NM_L$ decreases and $NM_H$ increases.
  3. Both $NM_L$ and $NM_H$ increase.
  4. No change in the noise margins.

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Show answer and explanation

Correct answer: (A) $NM_L$ increases and $NM_H$ decreases.

Explanation

A larger pMOS (larger $\beta_p/\beta_n$) moves the inverter switching threshold $V_M$ upwards. A higher threshold means $V_{IL}$ rises (so $NM_L=V_{IL}-V_{OL}$ increases) and $V_{IH}$ rises towards $V_{OH}$ (so $NM_H=V_{OH}-V_{IH}$ decreases).